1. Field of the Invention
The present invention relates to a memory system. More particularly, the present invention relates to a wrapper circuit for interfacing between a (non-muxed type) memory controller in which an address port and a data port are distinct from each other and a (muxed type) memory in which an address port and a data port are shared (time-multiplexed, not physically distinct from each other).
2. Description of the Related Art
A memory is a device that stores data. A memory may be classified as either a volatile memory or a nonvolatile memory. Volatile memories include dynamic random access memories (DRAM), static random access memories (SRAM). An example of a volatile memory includes a unitransistor random access memory (UtRAM). Examples of nonvolatile memories include a mask read only memory (ROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a flash memory, etc. In addition, a further examples of nonvolatile memories are a ferroelectric random access memory (FRAM), a phase-change random access memory (PRAM) and a magnetic random access memory (MRAM).
The memory types may be further divided into synchronous memories and asynchronous memories depending on whether an operation of the memory is synchronized to a clock signal or not. The asynchronous memory was used more often in the past, but the synchronous memories are more frequently used in recent designs. For example, an asynchronous type of the “NOR flash” memory was more often used in the past, while a synchronous type of “NOR flash” memory is more frequently used in recent years.
The memory chips (memory chip packages) used today have a lot of pins so as to implement various functions. However, equipping the memory with many pins increases the cost of manufacturing of a memory (chip) package and of implementing a system using the memory. Accordingly, efforts have been made to reduce the number of pins. Particularly, a technology in which an address port (address pins or lines) and a data port (data pins or lines) are shared (time-multiplexed, not distinct from each other) is now popular. This technology will be described in further detail with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram illustrating a memory system in which an address port and a data port are separate (distinct) from each other.
A memory 120 is used together with a memory controller 110 in a system. The memory controller 110 receives data through a system bus (not shown) and stores the received data in the memory 120. The memory controller 110 also receives the data stored in the memory and transfers the stored data to the system bus. In other words, the memory controller 110 interfaces between the memory 120 and the system bus.
The memory controller 110 provides control ports 130 (CSN, WEN, OEN, AVD, DATAEN) for accessing the memory 120, an address 140 for designating an access location on the memory 120, and data 150 to the memory 120. Also, the memory controller 110 receives the data 150 stored in a specific location of the memory 120 from the memory 120. In FIG. 1, in the memory controller 110 and the memory 120, a port for sending/receiving an address (140) and a port for sending/receiving data (150) are distinct (separate, non-multiplexed) from each other. The address 140 is outputted from an address port of the memory controller 110 and inputted to an address port of the memory 120. The data 150 (while writing data) is outputted from a data port of the memory controller 110 and inputted to a data port of the memory 120, and data 150 (while reading data) is outputted from the data port of the memory 120 and inputted to the data port of the memory controller 110.
FIG. 2 is a block diagram illustrating a memory system in which an address port and a data port are shared (time-multiplexed on the same pins, not distinct from each other).
A memory 220 is used together with a memory controller 210 in a system. The memory controller 210 receives data through a system bus and stores the data in the memory 220, or receives the data stored in the memory 220 and sends the data to the system bus (not shown).
The memory controller 210 sends control signals 230 for accessing the memory 220, an address for designating an access location on the memory 220, and writes data 240 to the memory 220. Further, the memory controller 210 receives read data 250 stored in a specific location of the memory 220 from the memory 220. In this case, both the memory controller 210 and the memory 220 use a shared (time-multiplexed on the same pins, not distinct from each other) address port and a write data port.
A non-multiplexed (non-muxed) type memory controller is required for a memory as in FIG. 1 in which the address port and the data port are distinct from each other (hereinafter referred to herein as “non-muxed type memory” and sometimes referred to as a “demuxed type memory”), and a muxed type memory controller is required for a memory as in FIG. 2 in which the address port and the data port are shared to each other (hereinafter referred to as “muxed type memory”). Meanwhile, the memories may be a non-muxed type (120 in FIG. 1) or a muxed type memory (220 in FIG. 2) depending on manufacturers and depending on the capacity of the memory.
Mobile devices are applications that use memory and are increasingly popular. Mobile devices preferably use a muxed type memory having a small number of memory pins. Accordingly, the conventional non-muxed type memory controller can not be used with the muxed type memory. Although it is possible that a muxed type controller suitable for the muxed type may be specially designed, the cost for manufacturing it is high. Accordingly, a logic circuit that controls the muxed type memory using the conventional non-muxed type memory controller has been required.